27/10/2024 - 02/11/2024

30/10/2024 22:37

I tried following this guide as a first step to using the microblaze to communicate wtih DDR3:
https://numato.com/kb/ddr3-memory-tests-on-nereid-k7-board/

Only the last part of the guide fails, my PuTTy terminal prints:

--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes

--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes

When it should print:

Somehow it's getting stuck communicating with the DDR3. I'm unsure why this is happening.

30/10/2024 22:48

Debugging with print statements tells me that this line is the culprit:

    status = Xil_TestMem32((u32*)range->base, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);

    status = Xil_TestMem32((u32*)range->base, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);

in this file (memorytest.c):

/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
 ******************************************************************************/

#include <stdio.h>
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_testmem.h"

#include "platform.h"
#include "memory_config.h"
#include "xil_printf.h"

/*
 * memory_test.c: Test memory ranges present in the Hardware Design.
 *
 * This application runs with D-Caches disabled. As a result cacheline requests
 * will not be generated.
 *
 * For MicroBlaze/PowerPC, the BSP doesn't enable caches and this application
 * enables only I-Caches. For ARM, the BSP enables caches by default, so this
 * application disables D-Caches before running memory tests.
 */

void putnum(unsigned int num);

void test_memory_range(struct memory_range_s *range) {
    XStatus status;

    /* This application uses print statements instead of xil_printf/printf
     * to reduce the text size.
     *
     * The default linker script generated for this application does not have
     * heap memory allocated. This implies that this program cannot use any
     * routines that allocate memory on heap (printf is one such function).
     * If you'd like to add such functions, then please generate a linker script
     * that does allocate sufficient heap memory.
     */

    print("Testing memory region: "); print(range->name);  print("\n\r");
    print("    Memory Controller: "); print(range->ip);  print("\n\r");
    #if defined(__MICROBLAZE__) && !defined(__arch64__)
        #if (XPAR_MICROBLAZE_ADDR_SIZE > 32)
            print("         Base Address: 0x"); putnum((range->base & UPPER_4BYTES_MASK) >> 32); putnum(range->base & LOWER_4BYTES_MASK);print("\n\r");
        #else
            print("         Base Address: 0x"); putnum(range->base); print("\n\r");
        #endif
        print("                 Size: 0x"); putnum(range->size); print (" \n\r");
    #else
        xil_printf("         Base Address: 0x%lx \n\r",range->base);
        xil_printf("                 Size: 0x%lx bytes \n\r",range->size);
    #endif

#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
    print("Performing tests (type 1)... \n\r");
    status = Xil_TestMem32((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem16((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem8((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");
#else
    print("Performing tests (type 2)... \n\r");
    status = Xil_TestMem32((u32*)range->base, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem16((u16*)range->base, 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem8((u8*)range->base, 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");
#endif

}

int main()
{
    sint32 i;

    init_platform();

    print("--Starting Memory Test Application--\n\r");
    print("NOTE: This application runs with D-Cache disabled.");
    print("As a result, cacheline requests will not be generated\n\r");

    for (i = 0; i < n_memory_ranges; i++) {
        test_memory_range(&memory_ranges[i]);
    }

    print("--Memory Test Application Complete--\n\r");
    print("Successfully ran Memory Test Application");
    cleanup_platform();
    return 0;
}

/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
 ******************************************************************************/

#include <stdio.h>
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_testmem.h"

#include "platform.h"
#include "memory_config.h"
#include "xil_printf.h"

/*
 * memory_test.c: Test memory ranges present in the Hardware Design.
 *
 * This application runs with D-Caches disabled. As a result cacheline requests
 * will not be generated.
 *
 * For MicroBlaze/PowerPC, the BSP doesn't enable caches and this application
 * enables only I-Caches. For ARM, the BSP enables caches by default, so this
 * application disables D-Caches before running memory tests.
 */

void putnum(unsigned int num);

void test_memory_range(struct memory_range_s *range) {
    XStatus status;

    /* This application uses print statements instead of xil_printf/printf
     * to reduce the text size.
     *
     * The default linker script generated for this application does not have
     * heap memory allocated. This implies that this program cannot use any
     * routines that allocate memory on heap (printf is one such function).
     * If you'd like to add such functions, then please generate a linker script
     * that does allocate sufficient heap memory.
     */

    print("Testing memory region: "); print(range->name);  print("\n\r");
    print("    Memory Controller: "); print(range->ip);  print("\n\r");
    #if defined(__MICROBLAZE__) && !defined(__arch64__)
        #if (XPAR_MICROBLAZE_ADDR_SIZE > 32)
            print("         Base Address: 0x"); putnum((range->base & UPPER_4BYTES_MASK) >> 32); putnum(range->base & LOWER_4BYTES_MASK);print("\n\r");
        #else
            print("         Base Address: 0x"); putnum(range->base); print("\n\r");
        #endif
        print("                 Size: 0x"); putnum(range->size); print (" \n\r");
    #else
        xil_printf("         Base Address: 0x%lx \n\r",range->base);
        xil_printf("                 Size: 0x%lx bytes \n\r",range->size);
    #endif

#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
    print("Performing tests (type 1)... \n\r");
    status = Xil_TestMem32((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem16((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem8((range->base & LOWER_4BYTES_MASK), ((range->base & UPPER_4BYTES_MASK) >> 32), 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");
#else
    print("Performing tests (type 2)... \n\r");
    status = Xil_TestMem32((u32*)range->base, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem16((u16*)range->base, 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");

    status = Xil_TestMem8((u8*)range->base, 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS? "PASSED!":"FAILED!"); print("\n\r");
#endif

}

int main()
{
    sint32 i;

    init_platform();

    print("--Starting Memory Test Application--\n\r");
    print("NOTE: This application runs with D-Cache disabled.");
    print("As a result, cacheline requests will not be generated\n\r");

    for (i = 0; i < n_memory_ranges; i++) {
        test_memory_range(&memory_ranges[i]);
    }

    print("--Memory Test Application Complete--\n\r");
    print("Successfully ran Memory Test Application");
    cleanup_platform();
    return 0;
}

There's some warning about casting a pointer to an integer of different size. Let me try to debug that?

30/10/2024 22:56

/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
 ******************************************************************************/

#include <stdio.h>
#include <stdint.h> // for uintptr_t
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_testmem.h"

#include "platform.h"
#include "memory_config.h"
#include "xil_printf.h"

/*
 * memory_test.c: Test memory ranges present in the Hardware Design.
 *
 * This application runs with D-Caches disabled. As a result cacheline requests
 * will not be generated.
 *
 * For MicroBlaze/PowerPC, the BSP doesn't enable caches and this application
 * enables only I-Caches. For ARM, the BSP enables caches by default, so this
 * application disables D-Caches before running memory tests.
 */

void putnum(unsigned int num);

void test_memory_range(struct memory_range_s *range) {
    XStatus status;

    print("Testing memory region: "); print(range->name);  print("\n\r");
    print("    Memory Controller: "); print(range->ip);  print("\n\r");

#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
    uintptr_t base_addr_lower = (uintptr_t)(range->base & LOWER_4BYTES_MASK);
    uintptr_t base_addr_upper = (uintptr_t)((range->base & UPPER_4BYTES_MASK) >> 32);

    print("         Base Address: 0x"); putnum(base_addr_upper); putnum(base_addr_lower); print("\n\r");
#else
    // Use uintptr_t for cross-platform pointer-compatible integer
    uintptr_t base_addr = (uintptr_t)range->base;
    xil_printf("         Base Address: 0x%lx \n\r", base_addr);
#endif
    print("                 Size: 0x"); putnum(range->size); print (" bytes\n\r");

    print("Performing tests (type 2)... \n\r");

    // Perform 32-bit test
    status = Xil_TestMem32((u32 *)base_addr, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");

    // Perform 16-bit test
    status = Xil_TestMem16((u16 *)base_addr, 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");

    // Perform 8-bit test
    status = Xil_TestMem8((u8 *)base_addr, 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");
}

int main()
{
    sint32 i;

    init_platform();

    print("--Starting Memory Test Application--\n\r");
    print("NOTE: This application runs with D-Cache disabled.");
    print("As a result, cacheline requests will not be generated\n\r");

    for (i = 0; i < n_memory_ranges; i++) {
        test_memory_range(&memory_ranges[i]);
    }

    print("--Memory Test Application Complete--\n\r");
    print("Successfully ran Memory Test Application");
    cleanup_platform();
    return 0;
}

/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
 ******************************************************************************/

#include <stdio.h>
#include <stdint.h> // for uintptr_t
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_testmem.h"

#include "platform.h"
#include "memory_config.h"
#include "xil_printf.h"

/*
 * memory_test.c: Test memory ranges present in the Hardware Design.
 *
 * This application runs with D-Caches disabled. As a result cacheline requests
 * will not be generated.
 *
 * For MicroBlaze/PowerPC, the BSP doesn't enable caches and this application
 * enables only I-Caches. For ARM, the BSP enables caches by default, so this
 * application disables D-Caches before running memory tests.
 */

void putnum(unsigned int num);

void test_memory_range(struct memory_range_s *range) {
    XStatus status;

    print("Testing memory region: "); print(range->name);  print("\n\r");
    print("    Memory Controller: "); print(range->ip);  print("\n\r");

#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
    uintptr_t base_addr_lower = (uintptr_t)(range->base & LOWER_4BYTES_MASK);
    uintptr_t base_addr_upper = (uintptr_t)((range->base & UPPER_4BYTES_MASK) >> 32);

    print("         Base Address: 0x"); putnum(base_addr_upper); putnum(base_addr_lower); print("\n\r");
#else
    // Use uintptr_t for cross-platform pointer-compatible integer
    uintptr_t base_addr = (uintptr_t)range->base;
    xil_printf("         Base Address: 0x%lx \n\r", base_addr);
#endif
    print("                 Size: 0x"); putnum(range->size); print (" bytes\n\r");

    print("Performing tests (type 2)... \n\r");

    // Perform 32-bit test
    status = Xil_TestMem32((u32 *)base_addr, 1024, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
    print("          32-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");

    // Perform 16-bit test
    status = Xil_TestMem16((u16 *)base_addr, 2048, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
    print("          16-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");

    // Perform 8-bit test
    status = Xil_TestMem8((u8 *)base_addr, 4096, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
    print("           8-bit test: "); print(status == XST_SUCCESS ? "PASSED!" : "FAILED!"); print("\n\r");
}

int main()
{
    sint32 i;

    init_platform();

    print("--Starting Memory Test Application--\n\r");
    print("NOTE: This application runs with D-Cache disabled.");
    print("As a result, cacheline requests will not be generated\n\r");

    for (i = 0; i < n_memory_ranges; i++) {
        test_memory_range(&memory_ranges[i]);
    }

    print("--Memory Test Application Complete--\n\r");
    print("Successfully ran Memory Test Application");
    cleanup_platform();
    return 0;
}

I changed the code to this to remove the warnings; but no luck. The output is the same.

30/10/2024 23:01

I discovered the ddr3 was not getting the correct clock signal (it was getting the "locked" signal from the clock wizard, not sure how that happened or how it even generated a bitstream). I've fixed the error and will try again.

30/10/2024 23:18

I tried creating the same project on the Linux Mint computer in the lab as Vivado runs faster on linux. However, I couldn't open vitis. I found one person who had the same issue as me with no explanation other than "this distro is not officially supported":
https://adaptivesupport.amd.com/s/question/0D54U00008mtLFpSAM/vitis-20232-exits-immediately-on-ubuntu-2404-no-error-messages-displayed?language=en_US

30/10/2024 23:26

I discovered the ddr3 was not getting the correct clock signal (it was getting the "locked" signal from the clock wizard, not sure how that happened or how it even generated a bitstream). I've fixed the error and will try again.

This fix ended up working:

--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes
          32-bit test: PASSED!
          16-bit test: PASSED!
           8-bit test: PASSED!
--Memory Test Application Complete--
Successfully ran Memory Test Application

--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes
          32-bit test: PASSED!
          16-bit test: PASSED!
           8-bit test: PASSED!
--Memory Test Application Complete--
Successfully ran Memory Test Application

31/10/2024 00:20

I cratred the following block design

I added a PCIe DMA bridge (XDMA) and an AXI smart connect to try to hook up M03A_XI of the microblaze axi periphereal and the PCIe DMA Bridge to the DDR3. This seems very naive to me. For instance, I don't know what the AXI smart connect does with the two clocks I put in. I also don't know if it's problematic that the aresetn port is linked to just the one provided by the PCIe DMA bridge when there is a arestn signal input from the microblaze to the microblaze peripheal for M03 which drives S00 of the AXI smart connect.

This design passes valdation on both my windows and linux systems I'm trying it on. It succesfully generates a bitstream on linux, but not windows. I don't know why.

The diagrams appear the same to me on window and linux but on windows I get this error:

[DRC REQP-1619] IBUFDS_GTE2_driven_by_IBUF: 
IBUFDS_GTE2 ddr3_i/util_ds_buf/U0/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I pins I and IB should be driven by IBUFs.

[DRC REQP-1619] IBUFDS_GTE2_driven_by_IBUF: 
IBUFDS_GTE2 ddr3_i/util_ds_buf/U0/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I pins I and IB should be driven by IBUFs.

looking it up it seems to be some gigabit transciever pad (whatever that means):
https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/IBUFDS_GTE2

I have no idea how that applies to this design. The only thing I can figure is the error is due to differences in vivado (windows is on 2022.3 while Linux is on 2023.2). Looking in the netlist after opening the synthesized design, the netlist is not the same. So the all the ports in the constraints file are not there (but are present in the linux case). Maybe that's the issue? Who knows

set_property -dict {PACKAGE_PIN K6} [get_ports pcie_refclk_clk_p]
set_property -dict {PACKAGE_PIN K5} [get_ports pcie_refclk_clk_n]
set_property -dict {PACKAGE_PIN R3} [get_ports {pcie_rxn[3]}]
set_property -dict {PACKAGE_PIN R4} [get_ports {pcie_rxp[3]}]
set_property -dict {PACKAGE_PIN N3} [get_ports {pcie_rxn[2]}]
set_property -dict {PACKAGE_PIN N4} [get_ports {pcie_rxp[2]}]
set_property -dict {PACKAGE_PIN L3} [get_ports {pcie_rxn[1]}]
set_property -dict {PACKAGE_PIN L4} [get_ports {pcie_rxp[1]}]
set_property -dict {PACKAGE_PIN J3} [get_ports {pcie_rxn[0]}]
set_property -dict {PACKAGE_PIN J4} [get_ports {pcie_rxp[0]}]

set_property -dict {PACKAGE_PIN P1} [get_ports {pcie_txn[3]}]
set_property -dict {PACKAGE_PIN P2} [get_ports {pcie_txp[3]}]
set_property -dict {PACKAGE_PIN M1} [get_ports {pcie_txn[2]}]
set_property -dict {PACKAGE_PIN M2} [get_ports {pcie_txp[2]}]
set_property -dict {PACKAGE_PIN K1} [get_ports {pcie_txn[1]}]
set_property -dict {PACKAGE_PIN K2} [get_ports {pcie_txp[1]}]
set_property -dict {PACKAGE_PIN H1} [get_ports {pcie_txn[0]}]
set_property -dict {PACKAGE_PIN H2} [get_ports {pcie_txp[0]}]

set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports pcie_reset]

set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS33} [get_ports red_blue_tri_o[0]]
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS33} [get_ports green]
set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS33} [get_ports red_blue_tri_o[1]]

set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property -dict {PACKAGE_PIN K6} [get_ports pcie_refclk_clk_p]
set_property -dict {PACKAGE_PIN K5} [get_ports pcie_refclk_clk_n]
set_property -dict {PACKAGE_PIN R3} [get_ports {pcie_rxn[3]}]
set_property -dict {PACKAGE_PIN R4} [get_ports {pcie_rxp[3]}]
set_property -dict {PACKAGE_PIN N3} [get_ports {pcie_rxn[2]}]
set_property -dict {PACKAGE_PIN N4} [get_ports {pcie_rxp[2]}]
set_property -dict {PACKAGE_PIN L3} [get_ports {pcie_rxn[1]}]
set_property -dict {PACKAGE_PIN L4} [get_ports {pcie_rxp[1]}]
set_property -dict {PACKAGE_PIN J3} [get_ports {pcie_rxn[0]}]
set_property -dict {PACKAGE_PIN J4} [get_ports {pcie_rxp[0]}]

set_property -dict {PACKAGE_PIN P1} [get_ports {pcie_txn[3]}]
set_property -dict {PACKAGE_PIN P2} [get_ports {pcie_txp[3]}]
set_property -dict {PACKAGE_PIN M1} [get_ports {pcie_txn[2]}]
set_property -dict {PACKAGE_PIN M2} [get_ports {pcie_txp[2]}]
set_property -dict {PACKAGE_PIN K1} [get_ports {pcie_txn[1]}]
set_property -dict {PACKAGE_PIN K2} [get_ports {pcie_txp[1]}]
set_property -dict {PACKAGE_PIN H1} [get_ports {pcie_txn[0]}]
set_property -dict {PACKAGE_PIN H2} [get_ports {pcie_txp[0]}]

set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports pcie_reset]

set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS33} [get_ports red_blue_tri_o[0]]
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS33} [get_ports green]
set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS33} [get_ports red_blue_tri_o[1]]

set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

31/10/2024 00:39

I exported the bitstream on the linux machine, and moved it over to vitis on the windows machine (yes this is a pain).

I see the following over the serial line via PuTTy:

NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes


NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x80000000 bytes

This is the same symptom I had before where the microblaze can't reach the ddr3 because it's improperly configured. This is expected considering what I wrote in the above note.

31/10/2024 14:23

It seems the correct question to ask at this point is "what is the best/proper way to connect two masters AXIs to a MIG IP block?

Multipel MIG blocks? Multiple master ports on the MIG? Here are some forum links:

A similar issue: https://adaptivesupport.amd.com/s/question/0D52E00006iHuLnSAK/multiple-mig-ips-or-multiple-controllers?language=en_US
Poor efficiency for this guy using a MIG with two clients: https://adaptivesupport.amd.com/s/question/0D52E00006hpk77SAA/poor-mig-effiency-for-multiple-clients?language=en_US
Evidence that the "number of controllers" is an artifact: https://adaptivesupport.amd.com/s/question/0D52E00006hpjL0SAI/bank-sharing-among-two-mig-controllers?language=en_US
Something about multiple data ports: https://adaptivesupport.amd.com/s/question/0D52E00006hpUwwSAE/how-can-i-get-more-that-1-application-port-in-7-series-mig?language=en_US
Multiport memory controller: https://docs.amd.com/v/u/en-US/xapp1164

I may also ask my own version of this question on some combination of the AMD support forums and Reddit r/FPGA forum.